Showing posts with label ASIC. Show all posts
Showing posts with label ASIC. Show all posts

Tuesday, May 8, 2007

Functional Coverage Plan? Directed Test Plan?

(This is for verification engineers)

With the new HVL, functional coverage plan is getting more and more popular. On one side the technology came up with great randomizer to solve the problem of engineers who use to generate all sitimuls from scratch. The new approach for verification was just to leave it to the randomizer and it will do the task of generating many scenarios with minimum code.

Today is that really true? Can we afford it for today's complex SoC? May be not, thats why we started giving directions to the randomizer with the help of functional coverage plan. Once we define the functional coverage plan then the randomizer will work towards the direction to meet the coverage goals. The randomizer hence gets directed from the cover points which we define. The quality of the functional coverage plan depends on the quality of the verification engineers. We might have the scenario where the team might reach 100% functional coverage but since the cover points where not fully defined it might be a false indication that the verification is complete.

Hence the key to this is to have a good verification engineer to give you a good quality of functional coverage plan, this sounds very similar or at least analogus to a good directed test plan. So does this means that we are back to the place where we need to make a good directed functional coverage plan (instead of calling it as directed test plan)?

Does this means that we are at the same point but just went a bit higher in terms of the level of abstraction for the verification plan?